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data sheet ics871002agi-02 revision a april 14, 2010 1 ?2010 integrated device technology, inc. differential-to-0.7v hcsl differential pci express? jitter attenuator ics871002i-02 general description the ics871002i-02 is a high performance jitter attenuator designed for use in pci express? systems. in some pci express systems, such as those found in desktop pcs, the pci express clocks are generated from a low bandwidth, high phase noise pll frequency synthesizer. in these systems, a jitte r attenuator may be required to attenuate high frequency random a nd deterministic jitter components from the pll synthesizer and from the system board. the ics871002i-02 has two pll bandwidth modes: 350khz and 2200khz. the 350khz mode provides the maximum jitter attenuation, but it also results in higher pll tracking time. in this mode, the spread spectrum modulation may also be attenuated. the 2200khz bandwidth provides the best tracking skew and will pass most spread profiles, but the jitter attenuation will not be as good as the lower bandwidth modes. the ics871002i-02 can be set for different modes using the f_selx pins as shown in table 3c. the ics871002i-02 uses idt 3 rd generation femtoclock tm pll technology to achieve the lowest possible phase noise. the device is packaged in a small 20 lead tssop package, making it ideal for use in space constrained applications such as pci express add-in cards. features ? two 0.7v hcsl differential output pairs ? one differential clock input ? clk, nclk can accept the following differential input levels: lvpecl, lvds, hstl, hcsl, sstl ? input frequency range: 98mhz to 128mhz ? output frequency range: 98mhz to 640mhz ? vco range: 490mhz - 640mhz ? cycle-to-cycle jitter : 45ps (maximum) ? two bandwidth modes allow the system designer to make jitter attenuation/tracking skew design trade-offs ? full 3.3v supply mode ? -40c to 85c ambient operating temperature ? available in both standard (rohs 5) and lead-free (rohs 6) packages pll bandwidth (typical) table hiperclocks? ic s bw_sel 0 = pll bandwidth: ~350khz (default) 1 = pll bandwidth: ~2200khz 5 (fixed) vco 490 - 640 mhz phase detector output divider 00 5 01 4 10 2 (default) 11 1 q0 nq0 q1 nq1 fb_ou t nfb_o u bw_sel clk nclk fb_in nfb_in f_sel[1:0] mr oe pulldown pullup:pulldown pulldown pullup pullup pulldown pullup pulldown 2 iref 0 = 350khz 1 = 2200khz 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 f_sel0 v dda f_sel1 bw_sel mr nfb_out fb_out iref nq0 v dd q0 v dd q1 nq1 nfb_in fb_in gnd nclk clk oe pin assignment ics871002i-02 20-lead tssop 6.5mm x 4.4mm x 0.925mm package body g package top view block diagram
ics871002i-02 data sheet pci express? jitter attenuator ics871002agi-02 revision a april 14, 2010 2 ?2010 integrated device technology, inc. table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics number name type description 1, 20 nq0, nq0 output differential output pair. hcsl interface levels. 2 iref input a fixed precision resistor (475 ? ) from this pin to ground provides a reference current used for differential current-mode qx/nqx clock outputs. 3, 4 fb_out, nfb_out output differential feedback output pair. hcsl interface levels. 5 mr input pulldown active high master reset. when logic high, the internal dividers are reset causing the true outputs (qx, fb_out) to go low and the inverted outputs (nqx, nfb_out) to go high. when logic low, th e internal dividers and the outputs are enabled. lvcmos/lvttl interface levels. 6 bw_sel input pulldown pll bandwidth select i nput. 0 = 350khz, 1 = 2200khz. see table 3b. 7, 9 f_sel1, f_sel0 input pullup pulldown frequency select pins. see table 3c . lvcmos/lvttl interface levels 8v dda power analog supply pin. 10, 19 v dd power core supply pins. 11 oe input pullup output enable pin. when high, the output s are active. when low, the outputs are in a high impedance state. lvcmos/l vttl interface levels. see table 3a. 12 clk input pulldown non-inverting differential clock input. 13 nclk input pullup inverting differential clock input. 14 gnd power power supply ground. 15 fb_in input pulldown non-inverting differential feedback clock input. 16 nfb_in input pullup inverting differential feedback clock input. 17, 18 nq1, q1 output differential output pair. hcsl interface levels. symbol parameter test conditions minimum typical maximum units c in input capacitance 4pf r pullup input pullup resistor 51 k ? r pulldown input pulldown resistor 51 k ?
ics871002i-02 data sheet pci express? jitter attenuator ics871002agi-02 revision a april 14, 2010 3 ?2010 integrated device technology, inc. function tables table 3a. output enable function table table 3b. pll bandwidth control table table 3c. f_selx function table input outputs oe q[1:0], nq[1:0] fb_out, nfb_out 0 high-impedance enabled 1 (default) enabled enabled input pll bandwidth bw_sel 0 350khz (default) 1 2200khz input frequency (mhz) inputs output frequency (mhz) f_sel1 f_sel0 divider 100 0 0 5 100 100 0 1 4 125 100 1 0 2 250 (default) 100 1 1 1 500
ics871002i-02 data sheet pci express? jitter attenuator ics871002agi-02 revision a april 14, 2010 4 ?2010 integrated device technology, inc. absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only . functional operation of product at t hese conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. lvds power supply dc characteristics, v dd = 3.3v 10%, t a = -40c to 85c table 4b. lvcmos/lvttl dc characteristics, v dd = 3.3v 10%, t a = -40c to 85c table 4c. differential dc characteristics, v dd = 3.3v 10%, t a = -40c to 85c note 1: v il should not be less than -0.3v. note 2: common mode input voltage is defined as v ih . item rating supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, v o -0.5v to v dd + 0.5v package thermal impedance, ja 86.7c/w (0 mps) storage temperature, t stg -65 c to 150 c symbol parameter test conditio ns minimum typical maximum units v dd core supply voltage 2.97 3.3 3.63 v v dda analog supply voltage v dd ? 0.12 3.3 v dd v i dd power supply current 75 ma i dda analog supply current 12 ma symbol parameter test conditions minimum typical maximum units v ih input high voltage 2 v dd + 0.3 v v il input low voltage -0.3 0.8 v i ih input high current oe, f_sel1 v dd = v in = 3.63v 5 a bw_sel, f_sel0, mr v dd = v in = 3.63v 150 a i il input low current oe, f_sel1 v dd = 3.63v, v in = 0v -150 a bw_sel, f_sel0, mr v dd = 3.63v, v in = 0v -5 a symbol parameter test conditions minimum typical maximum units i ih input high current clk, fb_in v dd = v in = 3.465v 150 a nclk, nfb_in v dd = v in = 3.465v 5 a i il input low current clk, fb_in v dd = 3.465v, v in = 0v -5 a nclk, nfb_in v dd = 3.465v, v in = 0v -150 a v pp peak-to-peak voltage; note 1 0.15 1.3 v v cmr common mode input voltage; note 1, 2 gnd + 0.5 v dd ? 0.85 v
ics871002i-02 data sheet pci express? jitter attenuator ics871002agi-02 revision a april 14, 2010 5 ?2010 integrated device technology, inc. table 5. 0.7v hcsl differential ac characteristics, v dd = 3.3v 10%, t a = -40c to 85c note: electrical parameters are guaranteed over the specified ambient operating temper ature range, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device wi ll meet specifications after th ermal equilibrium has been reached under these conditions. note: all parameters measured at f 250mhz unless noted otherwise. note 1: this parameter is defined in accordance with jedec standard 65. note 2: measurement taken from single ended waveform. note 3: defined as the maximum instantaneous voltage includi ng overshoot. see parameter measurement information section. note 4: defined as the minimum instantaneous voltage includ ing undershoot. see parameter measurement information section. note 5: measurement taken from differential waveform. note 6:t stable is the time the differential clock must maintain a minimum 150mv differential voltage after rising/falling edges before it i s allowed to drop back into the v rb 100mv differential range. note 7: measured at crossing point where the instantaneous voltage value of the rising edge of q equals the falling edge of nq. note 8: refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. refe rs to all crossing points for this measurement. note 9: defined as the total variation of all crossing voltages of rising q and falling nq, this is the maximum allowed varianc e in vcross for any particular system. note 10: input duty cycle must be 50%. symbol parameter test conditio ns minimum typical maximum units f max output frequency 98 640 mhz t jit(cc) cycle-to-cycle jitter; note 1 pll mode 45 ps v max absolute max. output voltage; note 2, 3 1150 mv v min absolute min. output voltage; note 2, 4 -300 mv v rb ringback voltage; note 5, 6 -100 100 mv v cross absolute crossing voltage; note 2, 7, 8 200 550 mv ? v cross total variation of v cross over all edges; note 2, 7, 9 140 mv t r / t f output rise/fall time measured between -150mv to +150mv 0.6 4.75 v/ns odc output duty cycle; note 10 48 52 %
ics871002i-02 data sheet pci express? jitter attenuator ics871002agi-02 revision a april 14, 2010 6 ?2010 integrated device technology, inc. parameter measureme nt information 3.3v hcsl output load ac test circuit differential input level differential measurement points for duty cycle/period 3.3v hcsl output load ac test circuit cycle-to-cycle jitter differential measurement points for ringback 475 ? measurement point 33 ? 50 ? 50 ? 33 ? measurement point 49.9 ? 49.9 ? hcsl gnd 2pf 2pf 0v iref v dda v dd 3.3v10% 3.3v10% nclk, clk, v dd gnd v cmr cross points v pp nfb_in fb_in clock period (differential) positive duty cycle (differential) negative duty cycle (differential) q - nq 0.0v 475 ? 50 ? 50 ? hcsl gnd 0v scope iref this load condition is used for i dd and tjit(cc) measurements. 3.3v10% v dda 3.3v10% v dd nq[0:1], nfb_out q[0:1], fb_out ? ? ? ? cycle n t cycle n+1 t jit(cc) = | t cycle n ? t cycle n+1 | 1000 cycles t st able t stable v rb v rb q - nq -150mv v rb = -100mv v rb = +100mv +150mv 0.0v
ics871002i-02 data sheet pci express? jitter attenuator ics871002agi-02 revision a april 14, 2010 7 ?2010 integrated device technology, inc. parameter measurement in formation, continued single-ended measurement points for absolute cross point and swing output rise/fall time single-ended measurement points for delta cross point nq q v cross_max = 550mv v cross_min = 250mv v max = 1.15v v min = -0.30v q - nq -150mv +150mv 0.0v fall edge rate rise edge rate q nq v cross_delta = 140mv
ics871002i-02 data sheet pci express? jitter attenuator ics871002agi-02 revision a april 14, 2010 8 ?2010 integrated device technology, inc. application information power supply filtering technique as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. to achieve optimum jitter performance, power supply isolation is requir ed. the ics871002i-02 provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v dd and v dda should be individually connected to the power supply plane through vias, and 0.01f bypass capacitors should be used for each pin. figure 1 illustrates this for a generic v dd pin and also shows that v dda requires that an additional 10 ? resistor along with a 10 f bypass capacitor be connected to the v dda pin. figure 1. power supply filtering wiring the differential input to accept single-ended levels figure 2 shows how a differential input can be wired to accept single ended levels. the reference voltage v ref = v dd /2 is generated by the bias resistors r1 and r2. the bypass capacitor (c1) is used to help filter noise on the dc bias. this bias circuit should be located as close to the input pin as possible. the ratio of r1 and r2 might need to be adjusted to position the v ref in the center of the input voltage swing. for example, if the input clock swing is 2.5v and v dd = 3.3v, r1 and r2 value should be adjusted to set v ref at 1.25v. the values below are for when both the single ended swing and v dd are at the same voltage. this configuration requ ires that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the input will attenuate the signal in half. this can be done in one of two ways. first, r3 and r4 in parallel should equal the transmission line impedance. for most 50 ? applications, r3 and r4 can be 100 ? . the values of the resistors can be increased to reduce the loading for slower and weaker lvcmos driver. when using single-ended signaling, the noise rejection bene fits of differential signaling are reduced. even though the differential input can handle full rail lvcmos signaling, it is recommended that the amplitude be reduced. the datasheet specifies a lower differential amplitude, however this only applies to differential signals. for single-ended applications, the swing can be larger, however v il cannot be less than -0.3v and v ih cannot be more than v dd + 0.3v. though some of the recommended components might not be used, the pads should be placed in the layout. they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a differential signal. figure 2. recommended schematic for wiring a diff erential input to accept single-ended levels v dd v dda 3.3v 10 ? 10f .01f .01f
ics871002i-02 data sheet pci express? jitter attenuator ics871002agi-02 revision a april 14, 2010 9 ?2010 integrated device technology, inc. differential clock input interface the clk /nclk accepts lvds, lvpecl, hstl, sstl, hcsl and other differential signals. the differential signal must meet the v pp and v cmr input requirements. figures 3a to 3f show interface examples for the clk/nclk input driven by the most common driver types. the input interfaces suggested here are examples only. please consult with the vendor of t he driver component to confirm the driver termination requirements. for example, in figure 3a, the input termination applies for idt open emitter hstl drivers. if you are using an hstl driver from another vendor, use their termination recommendation. 3a. clk/nclk input driven by an idt open emitter hstl driver figure 3c. clk/nclk input driven by a 3.3v lvpecl driver figure 3e. clk/nclk input driven by a 3.3v hcsl driver figure 3b. clk/nclk input driven by a 3.3v lvpecl driver figure 3d. clk/nclk input driven by a 3.3v lvds driver figure 3f. clk/nclk input dri ven by a 2.5v sstl driver r1 50 ? r2 50 ? 1.8v zo = 50 ? zo = 50 ? clk nclk 3.3v hstl idt hstl driver differential input r3 125 ? r4 125 ? r1 84 ? r2 84 ? 3.3v zo = 50 ? zo = 50 ? clk nclk 3.3v 3.3v lvpecl differential input hcsl *r3 33 ? *r4 33 ? clk nclk 3.3v 3.3v zo = 50 ? zo = 50 ? differential input r1 50 ? r2 50 ? *optional ? r3 and r4 can be 0 ? clk nclk differential input lvpecl 3.3v zo = 50 ? zo = 50 ? 3.3v r1 50 ? r2 50 ? r2 50 ? 3.3v r1 100 lvds clk nclk 3.3v receiver zo = 50 ? zo = 50 ? clk nclk differential input sstl 2.5v zo = 60 ? zo = 60 ? 2.5v 3.3v r1 120 ? r2 120 ? r3 120 ? r4 120 ?
ics871002i-02 data sheet pci express? jitter attenuator ics871002agi-02 revision a april 14, 2010 10 ?2010 integrated device technology, inc. recommendations for unused input and output pins inputs: lvcmos control pins all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. outputs: differential outputs all unused differential outputs can be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated. recommended termination figure 4a is the recommended termination for applications which require the receiver and driver to be on a separate pcb. all traces should be 50 ? impedance. figure 4a. recommended termination figure 4b is the recommended termination for applications which require a point to point connection and contain the driver and receiver on the same pcb. all traces should all be 50 ? impedance. figure 4b. recommended termination
ics871002i-02 data sheet pci express? jitter attenuator ics871002agi-02 revision a april 14, 2010 11 ?2010 integrated device technology, inc. schematic layout figure 5 shows an example of ics871002i-02 application schematic. in this example, the device is operated at v dd = 3.3v. the decoupling capacitors should be located as close as possible to the power pin. the input is driven by a 3.3v lvpec l driver. two examples of hcsl termination are shown in this schematic. figure 5. ics871002i-02 schematic layout vdd vdd fb_in nfb_in hcsl termination recommended for pci express add-in card vdd=3.3v nq0 ru2 not install ru1 1k rd2 1k rd1 not install vdd vdd u1 iref 2 fb_out 3 nfb_out 4 mr 5 bw_sel 6 f_sel1 7 vdda 8 f_sel0 9 vdd 10 oe 11 clk 12 nclk 13 gnd 14 fb_in 15 nfb_in 16 nq1 17 q1 18 vdd 19 q0 20 nq0 1 mr bw_sel f_sel0 f_sel1 nclk set logic input to '1' set logic input to '0' q0 to logic input pins to logic input pins logic control input examples nq1 c1 .1uf c4 .1uf recommended for pci express point-to-point connection lvpecl driv er zo = 50 ohm zo = 50 ohm r13 50 r12 50 r11 50 clk fb_in nfb_in r3 475 fb_in nfb_in + - r5 50 q1 zo = 50 zo = 50 + - r10 50 r1 33 zo = 50 zo = 50 r4 50 r9 50 r2 33 c2 10u r6 10 c3 0.1u vdda vdd oe r7 50 r8 50
ics871002i-02 data sheet pci express? jitter attenuator ics871002agi-02 revision a april 14, 2010 12 ?2010 integrated device technology, inc. power considerations this section provides information on power dissipa tion and junction temperature for the ics871002i-02. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics71002i-02 is the sum of th e core power plus the analog power plus the power dissipated i n the load(s). the following is the power dissipation for v dd = 3.3v + 10% = 3.63v, which gives worst case results. power (core) max = v dd_max * (i dd_max + i dda_max ) = 3.63v * (75ma + 12ma) = 315.81mw power (outputs) max = 46.8mw/loaded output pair if all outputs are loaded, the total power is 3 * 46.8mw = 140.4mw total power_ max (3.63v, with all outputs switching) = 315.81mw + 140.4mw = 456.21mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad dire ctly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the in ternal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the app ropriate junction-to-ambient thermal resistance ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 86.7c/w per table 6 below. therefore, tj for an ambient temperatur e of 85c with all outputs switching is: 85c + 0.456w * 86.7c/w = 124.6c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depend ing on the number of loaded ou tputs, supply voltage, air flow and the type of board (multi-layer). table 6. thermal resistance ja for 20 lead tssop, forced convection ja by velocity meters per second 012.5 multi-layer pcb, jedec standard te st boards 86.7c/w 82.4c/w 80.2c/w
ics871002i-02 data sheet pci express? jitter attenuator ics871002agi-02 revision a april 14, 2010 13 ?2010 integrated device technology, inc. the purpose of this section is to calculate power dissipation on the ic per hcsl output pair. hcsl output driver circuit and termination are shown in figure 6. figure 6. hcsl driver circuit and termination hcsl is a current steering output which sources a maximum of 17ma of current per output. to calculate worst case on-chip power dissipation, use the following equations which assume a 50 ? load to ground. the highest power dissipation occurs when v dd _ max . power = (v dd_max ? v out ) * i out , since v out ? i out * r l = (v dd_max ? i out * r l ) * i out = (3.6v ? 17ma * 50 ? ) * 17ma total power dissipation per output pair = 46.8mw v dd v out r l 50 ? ic i out = 17ma r ref = 475 ? 1%
ics871002i-02 data sheet pci express? jitter attenuator ics871002agi-02 revision a april 14, 2010 14 ?2010 integrated device technology, inc. reliability information table 7. ja vs. air flow table for a 20 lead tssop transistor count the transistor count for ics871002i-02 is: 1,704 package outline and package dimensions package outline - g suffix for 20 lead tssop table 8 package dimensions reference document: jedec publication 95, mo-153 ja by velocity meters per second 012.5 multi-layer pcb, jedec standard test boards 86.7c/w 82.4c/w 80.2c/w all dimensions in millimeters symbol minimum maximum n 20 a 1.20 a1 0.05 0.15 a2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 d 6.40 6.60 e 6.40 basic e1 4.30 4.50 e 0.65 basic l 0.45 0.75 0 8 aaa 0.10
ics871002i-02 data sheet pci express? jitter attenuator ics871002agi-02 revision a april 14, 2010 15 ?2010 integrated device technology, inc. ordering information table 9. ordering information note: parts that are ordered with an "lf" suffix to the part number are the pb-free configuration and are rohs compliant. part/order number marking package shipping packaging temperature 871002agi-02 ics71002ai02 20 lead tssop tube -40 c to 85 c 871002AGI-02T ics71002ai02 20 lead tssop 2500 tape & reel -40 c to 85 c 871002agi-02lf ics1002ai02l ?le ad-free? 20 lead tssop tube -40 c to 85 c 871002agi-02lft ics1002ai02l ?lead-fr ee? 20 lead tssop 2500 tape & reel -40 c to 85 c while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this produc t is intended for use in normal commercial and industrial applications. any other applications, su ch as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not aut horize or warrant any idt product for use in life support devices or critical medical instruments.
ics871002i-02 data sheet pci express? jitter attenuator disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the ri ght to modify the products and/or specif ications described herein at any time and at idt? s sole discretion. all information in this document, including descriptions of product features and performance, is s ubject to change without notice. performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. the informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idt?s products for any partic ular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt?s products are not intended for use in life support systems or similar devices where the failure or malfunction of an idt p roduct can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own ri sk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered tr ademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2010. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056

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